From: Mike Frysinger Date: Sat, 12 Feb 2011 19:37:32 +0000 (+0000) Subject: opcodes: blackfin: drop "GP" register X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43a6aa65fe40d7285ea0511f39d32638292e8d35;p=binutils-gdb.git opcodes: blackfin: drop "GP" register There never was a "GP" register, so punt it from the decode map. It's a hold over from a very old processor definition and never made it into actual silicon. Signed-off-by: Mike Frysinger --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index eebe2ba1b0f..fb34a84233a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2011-02-12 Mike Frysinger + + * bfin-dis.c (machine_registers): Delete REG_GP. + (reg_names): Delete "GP". + (decode_allregs): Change REG_GP to REG_LASTREG. + 2011-02-12 Mike Frysinger * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH, diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c index 85b793cb743..f624bac2bad 100644 --- a/opcodes/bfin-dis.c +++ b/opcodes/bfin-dis.c @@ -227,7 +227,7 @@ enum machine_registers REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S, REG_AQ, REG_V, REG_VS, REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0, - REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1, + REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, @@ -262,7 +262,7 @@ static const char * const reg_names[] = "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S", "AQ", "V", "VS", "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0", - "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1", + "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1", "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT", "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", @@ -423,7 +423,7 @@ static const enum machine_registers decode_allregs[] = REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, - REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS, + REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,