From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 19 Dec 2021 21:27:09 +0000 (+0000)
Subject: pass the mode (LOAD,EXECUTE,STORE) through ISACaller RADIX MMU
X-Git-Tag: sv_maxu_works-initial~619
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43a938b16d4f37c667406ba8898defc44db04551;p=openpower-isa.git

pass the mode (LOAD,EXECUTE,STORE) through ISACaller RADIX MMU
so that the right exception type can be raised (0x300 rather than 0x400)
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index f2a5aded..d3fb0ad4 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1026,7 +1026,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                 return
             elif e.args[0] == 'invalid':         # invalid
                # run a Trap but set DAR first
-                log ("RADIX MMU memory invalid error")
+                log ("RADIX MMU memory invalid error, mode %s" % e.mode)
                 self.call_trap(0x300, PIb.PRIV)    # 0x300, privileged
                 return
             # not supported yet:
diff --git a/src/openpower/decoder/isa/radixmmu.py b/src/openpower/decoder/isa/radixmmu.py
index 9fe724d9..afd84ea5 100644
--- a/src/openpower/decoder/isa/radixmmu.py
+++ b/src/openpower/decoder/isa/radixmmu.py
@@ -293,13 +293,14 @@ class RADIX:
 
     def ld(self, address, width=8, swap=True, check_in_mem=False,
                  instr_fetch=False):
-        print("RADIX: ld from addr 0x%x width %d" % (address, width))
-
-        priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
         if instr_fetch:
             mode = 'EXECUTE'
         else:
             mode = 'LOAD'
+        print("RADIX: ld from addr 0x%x width %d mode %s" % \
+               (address, width, mode))
+
+        priv = ~(self.msr[MSRb.PR].value) # problem-state ==> privileged
         addr = SelectableInt(address, 64)
         pte = self._walk_tree(addr, mode, priv)
 
@@ -444,7 +445,9 @@ class RADIX:
 
         # WIP
         if mbits == 0:
-            raise MemException("invalid")
+            exc = MemException("invalid")
+            exc.mode = mode
+            raise exc
 
         # mask_size := mbits(4 downto 0);
         mask_size = mbits[0:5]
@@ -487,7 +490,9 @@ class RADIX:
 
             print("    valid, leaf", valid, leaf)
             if not valid:
-                raise MemException("invalid")
+                exc = MemException("invalid")
+                exc.mode = mode
+                raise exc
             if leaf:
                 print ("is leaf, checking perms")
                 ok = self._check_perms(data, priv, mode)