From: Sebastien Bourdeauducq Date: Thu, 25 Apr 2013 18:19:49 +0000 (+0200) Subject: Remove undriven reset signals X-Git-Tag: 24jan2021_ls180~2967 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43ac5c847124fd2c131c3ead02c3c6f358c588b6;p=litex.git Remove undriven reset signals --- diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py index dcc2443e..be7f833f 100644 --- a/milkymist/dvisampler/clocking.py +++ b/milkymist/dvisampler/clocking.py @@ -13,8 +13,8 @@ class Clocking(Module, AutoCSR): self.serdesstrobe = Signal() self.clock_domains._cd_pix = ClockDomain() self.clock_domains._cd_pix5x = ClockDomain() - self.clock_domains._cd_pix10x = ClockDomain() - self.clock_domains._cd_pix20x = ClockDomain() + self.clock_domains._cd_pix10x = ClockDomain(reset_less=True) + self.clock_domains._cd_pix20x = ClockDomain(reset_less=True) ### diff --git a/milkymist/m1crg/__init__.py b/milkymist/m1crg/__init__.py index 7779cf4e..9e1511f6 100644 --- a/milkymist/m1crg/__init__.py +++ b/milkymist/m1crg/__init__.py @@ -13,7 +13,7 @@ class M1CRG(Module, AutoCSR): self.clock_domains.cd_sys4x_rd = ClockDomain() self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() - self.clock_domains.cd_vga = ClockDomain() + self.clock_domains.cd_vga = ClockDomain(reset_less=True) self.clk4x_wr_strb = Signal() self.clk4x_rd_strb = Signal()