From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Aug 2022 00:42:10 +0000 (+0100)
Subject: completely bungled multi-EXTRA specs
X-Git-Tag: sv_maxu_works-initial~185
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43b06b819839a3b84a76fb69a5b3690918e6b381;p=openpower-isa.git

completely bungled multi-EXTRA specs
https://bugs.libre-soc.org/show_bug.cgi?id=838#c9
should be d:RS;d:CR0, missing a semicolon. sigh
---

diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv
index ed1014c6..d1753d95 100644
--- a/openpower/isatables/LDSTRM-2P-2S1D.csv
+++ b/openpower/isatables/LDSTRM-2P-2S1D.csv
@@ -40,9 +40,9 @@ lwaux,LDST,,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0,RA
 lhaux,LDST,,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0,RA
 lfsux,LDST,,2P,EXTRA2,d:FRT,d:RA,s:RB,0,RA,RB,0,FRT,0,0,0,RA
 lfdux,LDST,,2P,EXTRA2,d:FRT,d:RA,s:RB,0,RA,RB,0,FRT,0,0,0,RA
-stdux,LDST,,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,RA
-stwux,LDST,,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,RA
-stbux,LDST,,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,RA
-sthux,LDST,,2P,EXTRA2,d:RA,s:RSs:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,RA
-stfsux,LDST,,2P,EXTRA2,d:RA,s:FRSs:RA,s:RB,0,RA,RB,FRS,0,0,0,0,RA
-stfdux,LDST,,2P,EXTRA2,d:RA,s:FRSs:RA,s:RB,0,RA,RB,FRS,0,0,0,0,RA
+stdux,LDST,,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,RA
+stwux,LDST,,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,RA
+stbux,LDST,,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,RA
+sthux,LDST,,2P,EXTRA2,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,RA
+stfsux,LDST,,2P,EXTRA2,d:RA,s:FRS;s:RA,s:RB,0,RA,RB,FRS,0,0,0,0,RA
+stfdux,LDST,,2P,EXTRA2,d:RA,s:FRS;s:RA,s:RB,0,RA,RB,FRS,0,0,0,0,RA
diff --git a/openpower/isatables/LDSTRM-2P-3S.csv b/openpower/isatables/LDSTRM-2P-3S.csv
index b6f78340..a557d3f4 100644
--- a/openpower/isatables/LDSTRM-2P-3S.csv
+++ b/openpower/isatables/LDSTRM-2P-3S.csv
@@ -13,7 +13,7 @@ sthcix,LDST,,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,0
 stbcix,LDST,,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,0
 stfiwx,LDST,,2P,EXTRA2,s:FRS,s:RA,s:RB,0,RA_OR_ZERO,RB,FRS,0,0,0,0,0
 stdcix,LDST,,2P,EXTRA2,s:RS,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,0,0
-stwcx,LDST,,2P,EXTRA2,s:RSd:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0,0
-stdcx,LDST,,2P,EXTRA2,s:RSd:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0,0
-stbcx,LDST,,2P,EXTRA2,s:RSd:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0,0
-sthcx,LDST,,2P,EXTRA2,s:RSd:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0,0
+stwcx,LDST,,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0,0
+stdcx,LDST,,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0,0
+stbcx,LDST,,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0,0
+sthcx,LDST,,2P,EXTRA2,s:RS;d:CR0,s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,CR0,0,0
diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index a1c978f8..d6dfa167 100644
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -567,7 +567,7 @@ def process_csvs(format):
                     res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
                     res['0'] = 'd:RA'  # RA: Rdest1_EXTRA2
                     # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2
-                    res['1'] = sRS+'s:RA'
+                    res['1'] = "%s;%s" % (sRS, 's:RA')
                     res['2'] = 's:RB'  # RB: Rsrc2_EXTRA2
                 elif 'u' in insn_name:  # ldux etc.
                     res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
@@ -583,7 +583,7 @@ def process_csvs(format):
             elif value == 'LDSTRM-2P-3S':
                 res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
                 if 'cx' in insn_name:
-                    res['0'] = sRS+dCR  # RS: Rsrc1_EXTRA2 CR0: dest
+                    res['0'] = "%s;%s" % (sRS, dCR) # RS: Rsrc1_EXTRA2 CR0: dest
                 else:
                     res['0'] = sRS  # RS: Rsrc1_EXTRA2
                 res['1'] = 's:RA'  # RA: Rsrc2_EXTRA2