From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 16:38:22 +0000 (+0000)
Subject: missed out assignment in new specallocate=True StageChain mode
X-Git-Tag: ls180-24jan2020~1414
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43bd03a3d440a5d82e860b30dd34a4fe72ce552b;p=ieee754fpu.git

missed out assignment in new specallocate=True StageChain mode
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index a5e00750..033536a6 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -374,6 +374,7 @@ class StageChain(StageCls):
                 if self.specallocate:
                     ni = self.chain[idx+1].ispec() # new input on next loop
                     m.d.comb += eq(ni, o)          # assign to next input
+                    i = ni
                 else:
                     i = o
         self.o = o                             # last loop is the output