From: Andreas Sandberg Date: Fri, 11 Sep 2020 18:01:44 +0000 (+0100) Subject: stats: Move global CPU stats to BaseCPU X-Git-Tag: develop-gem5-snapshot~763 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43cbcd93ac4aac0a607c3f40d76f99cdf4f37155;p=gem5.git stats: Move global CPU stats to BaseCPU We currently register global CPU statistics such as sim_insts and sim_ops from stat_control.cc. This adds an undesriable dependency on BaseCPU from stats_contro.cc. Move the CPU-specific stats to a global stat group in BaseCPU. This group is merged with the Root object's stats which means that they appear as global stats in a typical stat dump. Care has been taken to keep the old stat names. However, the order of the stats.txt will be slightly different due to the way legacy stats and new-style stats are serialised. Change-Id: I5410bc432f1a8cf3de58b08ca54a1aa2711d9c76 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34395 Reviewed-by: Jason Lowe-Power Reviewed-by: Daniel Carvalho Maintainer: Jason Lowe-Power Tested-by: kokoro --- diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 9ba1b315b..ef843d757 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012,2016-2017, 2019 ARM Limited + * Copyright (c) 2011-2012,2016-2017, 2019-2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -63,6 +63,7 @@ #include "sim/clocked_object.hh" #include "sim/full_system.hh" #include "sim/process.hh" +#include "sim/root.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" @@ -72,6 +73,8 @@ using namespace std; +std::unique_ptr BaseCPU::globalStats; + vector BaseCPU::cpuList; // This variable reflects the max number of threads in any CPU. Be @@ -370,6 +373,12 @@ BaseCPU::regStats() { ClockedObject::regStats(); + if (!globalStats) { + /* We need to construct the global CPU stat structure here + * since it needs a pointer to the Root object. */ + globalStats.reset(new GlobalStats(Root::root())); + } + using namespace Stats; numCycles @@ -754,3 +763,39 @@ BaseCPU::waitForRemoteGDB() const { return params()->wait_for_remote_gdb; } + + +BaseCPU::GlobalStats::GlobalStats(::Stats::Group *parent) + : ::Stats::Group(parent), + simInsts(this, "sim_insts", "Number of instructions simulated"), + simOps(this, "sim_ops", "Number of ops (including micro ops) simulated"), + hostInstRate(this, "host_inst_rate", + "Simulator instruction rate (inst/s)"), + hostOpRate(this, "host_op_rate", + "Simulator op (including micro ops) rate (op/s)") +{ + simInsts + .functor(BaseCPU::numSimulatedInsts) + .precision(0) + .prereq(simInsts) + ; + + simOps + .functor(BaseCPU::numSimulatedOps) + .precision(0) + .prereq(simOps) + ; + + hostInstRate + .precision(0) + .prereq(simInsts) + ; + + hostOpRate + .precision(0) + .prereq(simOps) + ; + + hostInstRate = simInsts / hostSeconds; + hostOpRate = simOps / hostSeconds; +} diff --git a/src/cpu/base.hh b/src/cpu/base.hh index c830576ad..9cf4baa7b 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -145,6 +145,23 @@ class BaseCPU : public ClockedObject /** Cache the cache line size that we get from the system */ const unsigned int _cacheLineSize; + /** Global CPU statistics that are merged into the Root object. */ + struct GlobalStats : public Stats::Group { + GlobalStats(::Stats::Group *parent); + + ::Stats::Value simInsts; + ::Stats::Value simOps; + + ::Stats::Formula hostInstRate; + ::Stats::Formula hostOpRate; + }; + + /** + * Pointer to the global stat structure. This needs to be + * constructed from regStats since we merge it into the root + * group. */ + static std::unique_ptr globalStats; + public: /** diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc index 075be5b05..5b667860b 100644 --- a/src/sim/stat_control.cc +++ b/src/sim/stat_control.cc @@ -53,10 +53,6 @@ #include "base/hostinfo.hh" #include "base/statistics.hh" #include "base/time.hh" -#include "config/the_isa.hh" -#if THE_ISA != NULL_ISA -#include "cpu/base.hh" -#endif #include "sim/global_event.hh" using namespace std; @@ -65,6 +61,7 @@ Stats::Formula simSeconds; Stats::Value simTicks; Stats::Value finalTick; Stats::Value simFreq; +Stats::Value hostSeconds; namespace Stats { @@ -97,42 +94,14 @@ statFinalTick() struct Global { - Stats::Formula hostInstRate; - Stats::Formula hostOpRate; Stats::Formula hostTickRate; Stats::Value hostMemory; - Stats::Value hostSeconds; - - Stats::Value simInsts; - Stats::Value simOps; Global(); }; Global::Global() { - simInsts - .name("sim_insts") - .desc("Number of instructions simulated") - .precision(0) - .prereq(simInsts) - ; - - simOps - .name("sim_ops") - .desc("Number of ops (including micro ops) simulated") - .precision(0) - .prereq(simOps) - ; - -#if THE_ISA != NULL_ISA - simInsts.functor(BaseCPU::numSimulatedInsts); - simOps.functor(BaseCPU::numSimulatedOps); -#else - simInsts.functor([] { return 0; }); - simOps.functor([] { return 0; }); -#endif - simSeconds .name("sim_seconds") .desc("Number of seconds simulated") @@ -157,20 +126,6 @@ Global::Global() "(restored from checkpoints and never reset)") ; - hostInstRate - .name("host_inst_rate") - .desc("Simulator instruction rate (inst/s)") - .precision(0) - .prereq(simInsts) - ; - - hostOpRate - .name("host_op_rate") - .desc("Simulator op (including micro ops) rate (op/s)") - .precision(0) - .prereq(simOps) - ; - hostMemory .functor(memUsage) .name("host_mem_usage") @@ -192,8 +147,6 @@ Global::Global() ; simSeconds = simTicks / simFreq; - hostInstRate = simInsts / hostSeconds; - hostOpRate = simOps / hostSeconds; hostTickRate = simTicks / hostSeconds; registerResetCallback([]() { diff --git a/src/sim/stats.hh b/src/sim/stats.hh index ed68af6ca..4e17f64f0 100644 --- a/src/sim/stats.hh +++ b/src/sim/stats.hh @@ -34,5 +34,6 @@ extern Stats::Formula simSeconds; extern Stats::Value simTicks; extern Stats::Value simFreq; +extern Stats::Value hostSeconds; #endif // __SIM_SIM_STATS_HH__