From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Oct 2018 13:34:07 +0000 (+0100)
Subject: add category descriptions
X-Git-Tag: convert-csv-opcode-to-binary~4946
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43d94bdb0b5dd9d3dd8c4e8398914ed3cb825bc3;p=libreriscv.git

add category descriptions
---

diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn
index 478eeb778..2241be015 100644
--- a/simple_v_extension/opcodes.mdwn
+++ b/simple_v_extension/opcodes.mdwn
@@ -18,7 +18,7 @@ indirectly adds on each RISC-V **standard** opcode.
   indirected) multi-register load operation where either or both of
   destination register or load-from-address register may be redirected,
   vectorised or **independently** predicated.
-* **vst**
+* **vst** - a matching multi-register store operation matching **vld**.
 * **VLU** - a "Unit Stride" variant of **vld** where instead of the
   source-address register number being (optionally) incremented
   (and redirected, and predicated) it is the **immediate offset**