From: whitequark <whitequark@whitequark.org>
Date: Sat, 26 Jan 2019 23:25:54 +0000 (+0000)
Subject: back.rtlil: accept ast.Const as cell parameter.
X-Git-Tag: working~31
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43e4833ddb5f36d8343ae830288eca221cec5fad;p=nmigen.git

back.rtlil: accept ast.Const as cell parameter.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index f85fcea..6fcd50b 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -114,9 +114,14 @@ class _ModuleBuilder(_Namer, _Bufferer):
             if isinstance(value, str):
                 self._append("    parameter \\{} \"{}\"\n",
                              param, value.translate(self._escape_map))
-            else:
+            elif isinstance(value, int):
                 self._append("    parameter \\{} {:d}\n",
                              param, value)
+            elif isinstance(value, ast.Const):
+                self._append("    parameter \\{} {}'{:b}\n",
+                             param, len(value), value.value)
+            else:
+                assert False
         for port, wire in ports.items():
             self._append("    connect {} {}\n", port, wire)
         self._append("  end\n")