From: Luke Kenneth Casson Leighton Date: Mon, 3 May 2021 15:28:14 +0000 (+0100) Subject: MMU: get store to activate only when data is available, and to wait till done X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43f240c1942c9f9b88c77d05fbc2d1591900d11f;p=soc.git MMU: get store to activate only when data is available, and to wait till done --- diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index fa10f642..812736d6 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -57,8 +57,6 @@ class LoadStore1(PortInterfaceBase): #m.d.comb += self.l_in.valid.eq(1) #m.d.comb += self.l_in.addr.eq(addr) #m.d.comb += self.l_in.load.eq(0) - m.d.comb += self.d_valid.eq(1) - m.d.comb += self.d_in.valid.eq(self.d_validblip) m.d.comb += self.d_in.load.eq(0) m.d.comb += self.d_in.byte_sel.eq(mask) m.d.comb += self.d_in.addr.eq(addr) @@ -87,12 +85,15 @@ class LoadStore1(PortInterfaceBase): return None #FIXME return value def set_wr_data(self, m, data, wen): + # do the "blip" on write data + m.d.comb += self.d_valid.eq(1) + m.d.comb += self.d_in.valid.eq(self.d_validblip) # put data into comb which is picked up in main elaborate() m.d.comb += self.d_w_valid.eq(1) m.d.comb += self.d_w_data.eq(data) #m.d.sync += self.d_in.byte_sel.eq(wen) # this might not be needed - #st_ok = self.d_out.valid # TODO indicates write data is valid - st_ok = Const(1, 1) + st_ok = self.d_out.valid # TODO indicates write data is valid + #st_ok = Const(1, 1) return st_ok def get_rd_data(self, m):