From: lkcl Date: Mon, 5 Sep 2022 09:48:50 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~693 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43f7e1add3cd4e5110c232a94cd6890a7f4e5167;p=libreriscv.git --- diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index b5ddcba94..bf3634b33 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -166,7 +166,7 @@ Core SVP64 instructions: Beyond this point are additional **Scalar** instructions related to specific workloads that have nothing to do with the SV Specification* -# Guarantees in Simple-V +# Stability Guarantees in Simple-V Providing long-term stability in an ISA is extremely challenging but critically important. @@ -181,14 +181,17 @@ It requires certain guarantees to be provided. * Fourthly, that any part of Simple-V not implemented by a lower Compliancy Level is *required* to raise an illegal instruction trap. +* Fifthly, that any `UNDEFINED` behaviour for practical implementation + reasons is clearly documented for both programmers and hardware + implementors. In particular, given the strong recent emphasis and interest in "Scalable Vector" ISAs, it is most unfortunate that both ARM SVE and RISC-V RVV permit the exact same instruction to produce different results on different hardware depending on a "Silicon Partner" hardware choice. This choice catastrophically -and irrevocably causes binary non-interoperability despite being -a "feature". Explained in +and irrevocably causes binary non-interoperability *despite being +a "feature"*. Explained in It is therefore *guaranteed* that extensions to the register file width and quantity in Simple-V shall only be made in future by