From: Michael Nolan Date: Mon, 8 Jun 2020 17:43:47 +0000 (-0400) Subject: Fix RC being set for stb and stbu X-Git-Tag: convert-csv-opcode-to-binary~2507 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43f8d9b8c1b7da189ab6139fdbbb1c807033af46;p=libreriscv.git Fix RC being set for stb and stbu --- diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv index effd8696c..076c31954 100644 --- a/openpower/isatables/major.csv +++ b/openpower/isatables/major.csv @@ -23,8 +23,8 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 20,SHIFT_ROT,OP_RLC,RA,CONST_SH32,RS,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi,M 21,SHIFT_ROT,OP_RLC,NONE,CONST_SH32,RS,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm,M 23,SHIFT_ROT,OP_RLC,NONE,RB,RS,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm,M -38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,1,stb,D -39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,RC,0,1,stbu,D +38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stb,D +39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbu,D 44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth,D 45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu,D 36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw,D