From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 18:54:34 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig
X-Git-Tag: working-ls180~1237^2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=440f173aef421f30c6ce63822532dbb8a1b231af;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig
---

440f173aef421f30c6ce63822532dbb8a1b231af
diff --cc CHANGELOG
index 73115600c,4d0c31e28..c280f4f12
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -22,11 -22,7 +22,12 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "muxcover -dmux=<cost>"
      - Added "muxcover -nopartial"
      - Added "muxpack" pass
+     - Added "pmux2shiftx -norange"
 +    - Added "write_xaiger" backend
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Added "synth -abc9" (experimental)
      - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
      - Fixed sign extension of unsized constants with 'bx and 'bz MSB