From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 21 Jun 2009 16:48:44 +0000 (-0700)
Subject: ARM: Get rid of unnecessary Re operand.
X-Git-Tag: Calvin_Submission~270
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4415e2dcd6ca508c4ffa8aa1fdcc53daee79b898;p=gem5.git

ARM: Get rid of unnecessary Re operand.
---

diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa
index bcb2869b7..e334f5521 100644
--- a/src/arch/arm/isa/bitfields.isa
+++ b/src/arch/arm/isa/bitfields.isa
@@ -70,8 +70,6 @@ def bitfield SHIFT_SIZE    <11: 7>;
 def bitfield SHIFT         < 6: 5>;
 def bitfield RM            < 3: 0>;
 
-def bitfield RE            <20:16>;
-
 def bitfield RS            <11: 8>;
 
 def bitfield RDUP          <19:16>;
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index f82e49109..be4ec6e03 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -46,7 +46,6 @@ def operands {{
     'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
     'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
-    'Re': ('IntReg', 'uw', 'RE', 'IsInteger', 5),
 
     'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
     'R0': ('IntReg', 'uw', '0', 'IsInteger', 5),