From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 3 Mar 2013 21:45:06 +0000 (+0100)
Subject: Fixed a gcc compiler warning [-Wparentheses]
X-Git-Tag: yosys-0.2.0~749
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=441e5fbfca9f32fd366dfaadc43ee7727141c2a4;p=yosys.git

Fixed a gcc compiler warning [-Wparentheses]
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 7c7d518dc..7d6c75150 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -139,12 +139,13 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
 	if (reg_wires.count(sig.chunks[0].wire->name) == 0)
 		return false;
 	reg_name = id(sig.chunks[0].wire->name);
-	if (sig.width != sig.chunks[0].wire->width)
+	if (sig.width != sig.chunks[0].wire->width) {
 		if (sig.width == 1)
 			reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset +  sig.chunks[0].offset);
 		else
 			reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset +  sig.chunks[0].offset + sig.chunks[0].width - 1,
 					sig.chunks[0].wire->start_offset +  sig.chunks[0].offset);
+	}
 	return true;
 }