From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Sat, 14 Nov 2020 15:22:34 +0000 (+0100)
Subject: sim._pyrtl: mask Mux selection operand.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44318149e00ccce6e63ba39361daff7ecc505bbe;p=nmigen.git

sim._pyrtl: mask Mux selection operand.

Otherwise it behaves funny when it's eg. the result of operator ~.
---

diff --git a/nmigen/sim/_pyrtl.py b/nmigen/sim/_pyrtl.py
index f7abc3b..3258f2b 100644
--- a/nmigen/sim/_pyrtl.py
+++ b/nmigen/sim/_pyrtl.py
@@ -177,7 +177,7 @@ class _RHSValueCompiler(_ValueCompiler):
         elif len(value.operands) == 3:
             if value.operator == "m":
                 sel, val1, val0 = value.operands
-                return f"({self(val1)} if {self(sel)} else {self(val0)})"
+                return f"({self(val1)} if {mask(sel)} else {self(val0)})"
         raise NotImplementedError("Operator '{}' not implemented".format(value.operator)) # :nocov:
 
     def on_Slice(self, value):
diff --git a/tests/test_sim.py b/tests/test_sim.py
index d2d255f..bb3906c 100644
--- a/tests/test_sim.py
+++ b/tests/test_sim.py
@@ -186,6 +186,11 @@ class SimulatorUnitTestCase(FHDLTestCase):
         self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(3, 4))
         self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(2, 4))
 
+    def test_mux_invert(self):
+        stmt = lambda y, a, b, c: y.eq(Mux(~c, a, b))
+        self.assertStatement(stmt, [C(2, 4), C(3, 4), C(0)], C(2, 4))
+        self.assertStatement(stmt, [C(2, 4), C(3, 4), C(1)], C(3, 4))
+
     def test_abs(self):
         stmt = lambda y, a: y.eq(abs(a))
         self.assertStatement(stmt, [C(3,  unsigned(8))], C(3,  unsigned(8)))