From: lkcl <lkcl@web>
Date: Sat, 9 Jan 2021 23:19:15 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~499
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=443a93905d71c135d0bf4783e61a0d181c60a62a;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 240962b5a..e019d9e9b 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -168,6 +168,7 @@ A summary of the effect of Vectorisation of src or dest:
      RA,RB    RT.s  RA/RB.s not vectorised
 
 Note that cache-inhibited LD/ST (`ldcix`) when VSPLAT is activated will perform **multiple** LD/ST operations, sequentially.  `ldcix` even with scalar src will read the same memory location *multiple times*, storing the result in successive Vector destination registers.  This because the cache-inhibit instructions are used to read and write memory-mapped peripherals.
+If a genuine VSPLAT is required then a scalar cache-inhibited LD should be performed, followed by a VSPLAT-augmented mv.
 
 # LOAD/STORE Elwidths <a name="ldst"></a>