From: Jacob Lifshay Date: Fri, 21 Apr 2023 00:35:37 +0000 (-0700) Subject: reformat list X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44437f9ee605322b2b383f537d0549325a7e0fab;p=libreriscv.git reformat list --- diff --git a/openpower/sv/rfc/ls013.mdwn b/openpower/sv/rfc/ls013.mdwn index 8757fab6b..2c7d14005 100644 --- a/openpower/sv/rfc/ls013.mdwn +++ b/openpower/sv/rfc/ls013.mdwn @@ -65,18 +65,17 @@ instruction in order to effectively implement Reduce-Min/Max. **Notes and Observations**: 1. SVP64 REMAP Parallel Reduction needs a single Scalar instruction to - work with, for best effectiveness. With no SFFS minimum/maximum instructions - Simple-V min/max Parallel Reduction is severely compromised. -2. Once one FP min/max mode is implemented the rest are not much more - hardware. -3. There exists similar instructions in VSX (not IEEE754-2019 though). - This is frequently used to justify not - adding them. However SVP64/VSX may have different meaning from SVP64/SFFS, - so it is *really* crucial to have SFFS ops even if "equivalent" to VSX - in order for SVP64 to not be compromised (non-orthogonal). + work with, for best effectiveness. With no SFFS minimum/maximum + instructions Simple-V min/max Parallel Reduction is severely compromised. +2. Once one FP min/max mode is implemented the rest are not much more hardware. +3. There exists similar instructions in VSX (not IEEE754-2019 though). + This is frequently used to justify not adding them. However SVP64/VSX may + have different meaning from SVP64/SFFS, so it is *really* crucial to have + SFFS ops even if "equivalent" to VSX in order for SVP64 to not be + compromised (non-orthogonal). 4. FP min/max are rather complex to implement in software, the most commonly - used FP max function `fmax` from glibc compiled for SFFS is an - astounding 32 instructions. + used FP max function `fmax` from glibc compiled for SFFS is an astounding + 32 instructions. **Changes**