From: lkcl <lkcl@web>
Date: Sat, 22 Apr 2023 00:05:10 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=445c2dcae59f1fc8042c91905a951ce18ea066db;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index ea6d17b0a..f57d8e6c9 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -574,6 +574,18 @@ Where this breaks down is when attempting to do half-width on
 BF16 or FP16 operations: there does not exist a BF8 or an IEEE754 FP8
 format, so these (`sv.fadds/ew=8`) should be avoided.
 
+# Word frequently becomes "half"
+
+Again, related to "Single" becoming "half of element width", unless there
+are compelling reasons the same trick applies to Scalar GPR operations.
+With the pseudocode being "XLEN//2" then of course if XLEN=8 the operation
+becomes a 4-bit one.
+
+Similarly byte operations which use "XLEN//8" when XLEN=8 actually become
+single-bit operations, which is very useful with `sv.extsb/w=8`
+for example.  This instruction copies the LSB of each byte in a sequence of bytes,
+and expands it to all 8 bits in each result byte.
+
 # Vertical-First and Subvectors
 
 Documented in the [[sv/setvl]] page, Vertical-First goes through