From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Apr 2019 09:28:35 +0000 (+0100)
Subject: call ControlBase elaborate from UnbufferedPipeline
X-Git-Tag: ls180-24jan2020~1336
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=446191ccc92a3efb51031ea7e13c9e7cd802dfea;p=ieee754fpu.git

call ControlBase elaborate from UnbufferedPipeline
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 4d285ad0..415f4b75 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -675,14 +675,14 @@ class UnbufferedPipeline(ControlBase):
         self.n.o_data = stage.ospec() # output type
 
     def elaborate(self, platform):
-        self.m = Module()
+        self.m = ControlBase.elaborate(self, platform)
 
         data_valid = Signal() # is data valid or not
         r_data = self.stage.ispec() # input type
         if hasattr(self.stage, "setup"):
             self.stage.setup(self.m, r_data)
 
-        # some temporarie
+        # some temporaries
         p_i_valid = Signal(reset_less=True)
         pv = Signal(reset_less=True)
         self.m.d.comb += p_i_valid.eq(self.p.i_valid_logic())