From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 7 Jan 2018 15:35:22 +0000 (+0100)
Subject: Bugfix in hierarchy blackbox module port width handling
X-Git-Tag: yosys-0.8~235
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=446ccf1f05b2b36db9161bf4ab050778a1cbaee6;p=yosys.git

Bugfix in hierarchy blackbox module port width handling
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index c680dbbd8..898763c64 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -621,8 +621,9 @@ struct HierarchyPass : public Pass {
 		}
 
 		std::set<Module*> blackbox_derivatives;
+		std::vector<Module*> design_modules = design->modules();
 
-		for (auto module : design->modules())
+		for (auto module : design_modules)
 		for (auto cell : module->cells())
 		{
 			Module *m = design->module(cell->type);