From: Tom Stellard <thomas.stellard@amd.com>
Date: Tue, 4 Sep 2012 15:20:01 +0000 (-0400)
Subject: radeon/llvm: Fix lowering of SI_V_CNDLT
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=446d19c12a576e36c3da34ada01b708fcbc196c5;p=mesa.git

radeon/llvm: Fix lowering of SI_V_CNDLT

SREG_LIT_0 is a scalar register, so it can only be used in the
first argument of vector instructoins.
---

diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp
index a64e2a378ff..2c8167382c7 100644
--- a/src/gallium/drivers/radeon/SIISelLowering.cpp
+++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
@@ -235,10 +235,10 @@ void SITargetLowering::LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB,
 void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
     MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
 {
-  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_LT_F32_e32),
+  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_GT_F32_e32),
           AMDGPU::VCC)
-          .addOperand(MI->getOperand(1))
-          .addReg(AMDGPU::SREG_LIT_0);
+          .addReg(AMDGPU::SREG_LIT_0)
+          .addOperand(MI->getOperand(1));
 
   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32))
           .addOperand(MI->getOperand(0))