From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Apr 2019 08:05:21 +0000 (+0100)
Subject: add example stage data signalling properties
X-Git-Tag: ls180-24jan2020~1339
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4472201afe414dfe5f8f69db179e187d8dbfa19b;p=ieee754fpu.git

add example stage data signalling properties
---

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 2376f337..6f43ba2b 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -594,11 +594,13 @@ class ExampleStageDelayCls(StageCls):
     def ospec(self):
         return Signal(16, name="example_output_signal")
 
-    def p_o_ready(self, m, p_in, p_out):
-        m.d.comb += p_out.eq(p_in)
+    @property
+    def p_o_ready(self):
+        return Const(1)
 
-    def n_o_valid(self, m, n_in, n_out):
-        m.d.comb += n_out.eq(n_in)
+    @property
+    def n_o_valid(self):
+        return Const(1)
 
     def process(self, i):
         """ process the input data and returns it (adds 1)