From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 18:00:27 +0000 (-0700)
Subject: Add support for CEP
X-Git-Tag: working-ls180~1039^2~198
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=447a31e75d7bd77c0108eb0c76b9749340b10db4;p=yosys.git

Add support for CEP
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 5ae34a1f7..a497d0a48 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -41,6 +41,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 	log("postAdd:    %s\n", log_id(st.postAdd, "--"));
 	log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
 	log("ffP:        %s\n", log_id(st.ffP, "--"));
+	log("ffPmux:     %s\n", log_id(st.ffPmux, "--"));
 #endif
 
 	log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
@@ -112,34 +113,32 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 			cell->setParam("\\BREG", 1);
 		}
 		if (st.ffM) {
-			SigSpec D = st.ffM->getPort("\\D");
-			SigSpec Q = st.ffM->getPort("\\Q");
-			P.replace(pm.sigmap(D), Q);
-			cell->setParam("\\MREG", State::S1);
 			if (st.ffMmux) {
 				cell->setPort("\\CEM", st.ffMmux->getPort("\\S"));
 				pm.autoremove(st.ffMmux);
 			}
 			else
 				cell->setPort("\\CEM", State::S1);
+			SigSpec D = st.ffM->getPort("\\D");
+			SigSpec Q = st.ffM->getPort("\\Q");
+			P.replace(/*pm.sigmap*/(D), Q);
+
+			cell->setParam("\\MREG", State::S1);
 			pm.autoremove(st.ffM);
 		}
 		if (st.ffP) {
-			SigSpec D;
-			//if (st.muxP)
-			//	D = st.muxP->getPort("\\B");
-			//else
-				D = st.ffP->getPort("\\D");
-			SigSpec Q = st.ffP->getPort("\\Q");
-			P.replace(pm.sigmap(D), Q);
-			cell->setParam("\\PREG", State::S1);
-			if (st.ffP->type == "$dff")
+			if (st.ffPmux) {
+				cell->setPort("\\CEP", st.ffPmux->getPort("\\S"));
+				st.ffPmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
+			}
+			else
 				cell->setPort("\\CEP", State::S1);
-			//else if (st.ffP->type == "$dffe")
-			//	cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
-			else log_abort();
-
+			SigSpec D = st.ffP->getPort("\\D");
+			SigSpec Q = st.ffP->getPort("\\Q");
+			P.replace(/*pm.sigmap*/(D), Q);
 			st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
+
+			cell->setParam("\\PREG", State::S1);
 		}
 
 		log("  clock: %s (%s)", log_signal(st.clock), "posedge");
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 2681cdbca..a2a6f2ef0 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -2,7 +2,7 @@ pattern xilinx_dsp
 
 state <SigBit> clock
 state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
-state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB postAddAB postAddMuxAB
+state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
 
 match dsp
 	select dsp->type.in(\DSP48E1)
@@ -120,7 +120,7 @@ match ffMmux
 	filter port(ffMmux, AB) == sigM.extract(0, GetSize(port(ffMmux, \Y)))
 	filter nusers(sigM.extract_end(GetSize(port(ffMmux, AB)))) <= 1
 	set ffMmuxAB AB
-	optional
+	semioptional
 endmatch
 
 code sigM
@@ -199,6 +199,22 @@ code sigC sigP
 	}
 endcode
 
+match ffPmux
+	select ffPmux->type.in($mux)
+	select nusers(port(ffPmux, \Y)) == 2
+	filter GetSize(port(ffPmux, \Y)) <= GetSize(sigP)
+	choice <IdString> AB {\A, \B}
+	filter port(ffPmux, AB) == sigP.extract(0, GetSize(port(ffPmux, \Y)))
+	filter nusers(sigP.extract_end(GetSize(port(ffPmux, AB)))) <= 1
+	set ffPmuxAB AB
+	semioptional
+endmatch
+
+code sigP
+	if (ffPmux)
+		sigP = port(ffPmux, \Y);
+endcode
+
 match ffP
 	if param(dsp, \PREG).as_int() == 0
 	select ffP->type.in($dff)
@@ -207,6 +223,8 @@ match ffP
 	filter GetSize(port(ffP, \D)) >= GetSize(sigP)
 	slice offset GetSize(port(ffP, \D))
 	filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) && port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
+	// Check ffPmux (when present) is a $dff enable mux
+	filter !ffPmux || port(ffP, \Q) == port(ffPmux, ffPmuxAB == \A ? \B : \A)
 	optional
 endmatch