From: Luke Kenneth Casson Leighton Date: Mon, 3 Jan 2022 23:37:28 +0000 (+0000) Subject: doh, bus-hack was the wrong way round. *output* the address with X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44854be174b951a3cc8aa62f0d5490b377ba0696;p=soc.git doh, bus-hack was the wrong way round. *output* the address with 3 extra LSBs at the front to fix the wishbone incompatibility --- diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index d75b1f5e..0ba9e8a0 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -363,8 +363,8 @@ class TestIssuerBase(Elaboratable): if self.microwatt_compat: ibus = self.imem.ibus dbus = self.core.l0.cmpi.wb_bus() - comb += ibus.adr.eq(self.ibus_adr[3:]) - comb += dbus.adr.eq(self.dbus_adr[3:]) + comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr)) + comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr)) cur_state = self.cur_state