From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 11 Aug 2020 13:37:51 +0000 (+0100)
Subject: reduce regfile port usage for INT and FAST
X-Git-Tag: semi_working_ecp5~399
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4493d96de291e27650d07fc746a11c5d01063586;p=soc.git

reduce regfile port usage for INT and FAST
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 20826b76..c3abdf00 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -68,7 +68,8 @@ class IntRegs(RegFileArray):
     def __init__(self):
         super().__init__(64, 32)
         self.w_ports = {'o': self.write_port("dest1"),
-                        'o1': self.write_port("dest2")} # for now (LD/ST update)
+                        #'o1': self.write_port("dest2") # for now (LD/ST update)
+                        }
         self.r_ports = {'ra': self.read_port("src1"),
                         'rbc': self.read_port("src3"),
                         'dmi': self.read_port("dmi")} # needed for Debug (DMI)
@@ -93,7 +94,6 @@ class FastRegs(RegFileArray):
     def __init__(self):
         super().__init__(64, 5)
         self.w_ports = {'fast1': self.write_port("dest3"),
-                        'fast2': self.write_port("dest4"),
                        }
         self.r_ports = {'fast1': self.read_port("src1"),
                         }
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index de5fa6cd..7da86929 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -366,6 +366,15 @@ class NonProductionCore(Elaboratable):
         for regfile, spec in byregfiles_wr.items():
             fuspecs = byregfiles_wrspec[regfile]
             wrpickers[regfile] = {}
+
+            # argh, more port-merging
+            if regfile == 'INT':
+                fuspecs['o'] = [fuspecs.pop('o')]
+                fuspecs['o'].append(fuspecs.pop('o1'))
+            if regfile == 'FAST':
+                fuspecs['fast1'] = [fuspecs.pop('fast1')]
+                fuspecs['fast1'].append(fuspecs.pop('fast2'))
+
             for (regname, fspec) in sort_fuspecs(fuspecs):
                 self.connect_wrport(m, fu_bitdict, wrpickers,
                                         regfile, regname, fspec)