From: Gabriel L. Somlo <gsomlo@gmail.com>
Date: Wed, 27 Mar 2019 20:38:25 +0000 (-0400)
Subject: soc/interconnect/axi: data/address length cleanup
X-Git-Tag: 24jan2021_ls180~1356^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=449632e43012bee423c23e634cedf7e3f4ce8696;p=litex.git

soc/interconnect/axi: data/address length cleanup

Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
---

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index a110c36d..17d431e6 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -60,12 +60,12 @@ class AXIInterface(Record):
 
 class AXI2Wishbone(Module):
     def __init__(self, axi, wishbone, base_address):
-        assert axi.data_width    == 32
-        assert axi.address_width == 32
+        assert axi.data_width    == len(wishbone.dat_r)
+        assert axi.address_width == len(wishbone.adr) + 2
 
         _data       = Signal(axi.data_width)
-        _read_addr  = Signal(32)
-        _write_addr = Signal(32)
+        _read_addr  = Signal(axi.address_width)
+        _write_addr = Signal(axi.address_width)
 
         self.comb += _read_addr.eq(axi.ar.addr - base_address)
         self.comb += _write_addr.eq(axi.aw.addr - base_address)