From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Sun, 3 Dec 2023 15:33:17 +0000 (+0000)
Subject: fosdem2024: add draft schedule.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=449ca9a2e520e969c063784fe2b07acb6d5cbb06;p=libreriscv.git

fosdem2024: add draft schedule.
---

diff --git a/conferences/fosdem2024/fosdem2024_schedule.mdwn b/conferences/fosdem2024/fosdem2024_schedule.mdwn
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+# (DRAFT) Devroom Schedule
+
+## Points of note
+
+- Tobias requested 60 min. Unfortunately there simply isn't enough time, thus
+Tobias will need to condense his talk down to 30min (or shorter). Assuming
+Tobias adjusts the time down to 30 min (25+5), **we need to find another 20min
+of time**.
+- Q&As are being used as breaks (only explicit break is between Sadoon's
+talks).
+- I (Andrey) have reduced the length of my talks to 10+5 and 15+5 respectively. I kept Cesar's talk at full 25+5 to make he has enough time to cover formal verification.
+
+## (Draft) Schedule for Saturday
+
+|Time |Talk|Speaker|Comments|
+|-----|----|-------|--------|
+|10:30|Overview of LibreSOC|Andrey||
+|     ||||
+|     |Q&A|||
+|10:45|Cologne Chip GateMate FPGA -- filling a gap between hardware and software (with a presentation of the GMM-7550 module)|Anton Kuzmin||
+|     ||||
+|     ||||
+|11:00||||
+|     ||||
+|     |Q&A|||
+|11:15|Introduction to SimpleV and PowerISA+SVP64|Andrey||
+|     ||||
+|     ||||
+|11:30|Q&A|||
+|     |Cryptographic Algorithm Vectorization for Mortals|Sadoon||
+|     ||||
+|11:45||||
+|     ||||
+|     ||||
+|12:00|Q&A|||
+|     |Break|||
+|     |Linux Distribution Porting for Architecture Subsets - 20+5 min|Sadoon||
+|12:15||||
+|     ||||
+|     ||||
+|12:30|Q&A|||
+|     |Advanced Simple-V: Data-dependent Fail-First|Luke||
+|     ||||
+|12:45||||
+|     ||||
+|     ||||
+|13:00|Q&A|||
+|     |How to write code for an experimental ISA like SVP64?|Konstantinos||
+|     ||||
+|13:15||||
+|     ||||
+|     ||||
+|13:30|Q&A|||
+|     |How to Commercialise Open-Source Work as a Business - Example LibreSOC and RED|James||
+|     ||||
+|13:45|Q&A|||
+|     |An introduction to Formal Verification of Digital Circuits|Cesar||
+|     ||||
+|14:00||||
+|     ||||
+|     ||||
+|14:15|Q&A|||
+|     |Using the ECP5 for Libre-SOC prototyping|Tobias||
+|     ||||
+|**14:30**||||
+
+