From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 17 Jan 2022 11:59:56 +0000 (+0000)
Subject: add pause_dec_tb signal (not very sophisticated) to Core
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44a11285f257bc65131805961ff947b51e25397a;p=soc.git

add pause_dec_tb signal (not very sophisticated) to Core
TODO, detect MTSPR and DEC/TB SPR being written to, but for now just
detect an entire SPR pipeline
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 74d96a87..8df7e17a 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -218,6 +218,10 @@ class NonProductionCore(ControlBase):
         if "mmu0" in self.decoders:
             self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
 
+        # allow pausing of the DEC/TB FSM back in Issuer, by spotting
+        # if there is an MTSPR instruction
+        self.pause_dec_tb = Signal()
+
     # next 3 functions are Stage API Compliance
     def setup(self, m, i):
         pass
@@ -511,6 +515,13 @@ class NonProductionCore(ControlBase):
                     funame.lower().startswith('trap')):
                     with m.If(fu.busy_o):
                         comb += busy_o.eq(1)
+                # for SPR pipeline pause dec/tb FSM to avoid race condition
+                # TODO: really this should be much more sophisticated,
+                # spot MTSPR, spot that DEC/TB is what is to be updated.
+                # a job for PowerDecoder2, there
+                if funame.lower().startswith('spr'):
+                    with m.If(fu.busy_o):
+                        comb += self.pause_dec_tb.eq(1)
 
         # return both the function unit "enable" dict as well as the "busy".
         # the "busy-or-issued" can be passed in to the Read/Write port