From: Konstantinos Margaritis <konstantinos.margaritis@vectorcamp.gr>
Date: Wed, 19 Jul 2023 16:49:51 +0000 (+0000)
Subject: Unify XLEN =64 special case in the new code
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44b15b4360ad3d9aa1e2cd2d7ccd64f6a99c4e4a;p=openpower-isa.git

Unify XLEN =64 special case in the new code
---

diff --git a/openpower/isa/butterfly.mdwn b/openpower/isa/butterfly.mdwn
index b6b7efe5..a1825ad8 100644
--- a/openpower/isa/butterfly.mdwn
+++ b/openpower/isa/butterfly.mdwn
@@ -21,36 +21,19 @@ Pseudo-code:
         RT <- prod1_lo
         RS <- prod2_lo
     else
-        if XLEN = 64 then
-            prod1_lo <- prod1[XLEN:(XLEN*2)-1]
-            prod2_lo <- prod2[XLEN:(XLEN*2)-1]
-            round <- [0]*XLEN
-            round[XLEN -n] <- 1
-            prod1_lo <- prod1_lo + round
-            prod2_lo <- prod2_lo + round
-            m <- MASK(n, (XLEN-1))
-            res1 <- ROTL64(prod1_lo, XLEN-n) & m
-            res2 <- ROTL64(prod2_lo, XLEN-n) & m
-            signbit1 <- prod1_lo[0]
-            signbit2 <- prod2_lo[0]
-            smask1 <- ([signbit1]*XLEN) & ¬m
-            smask2 <- ([signbit2]*XLEN) & ¬m
-            RT <- (res1 | smask1)
-            RS <- (res2 | smask2)
-        else
-            round <- [0]*(XLEN*2)
-            round[XLEN*2 -n] <- 1
-            prod1 <- prod1 + round
-            prod2 <- prod2 + round
-            m <- MASK(XLEN-n, XLEN-1)
-            res1 <- prod1[XLEN-n:XLEN*2 -n -1]
-            res2 <- prod2[XLEN-n:XLEN*2 -n -1]
-            signbit1 <- prod1[0]
-            signbit2 <- prod2[0]
-            smask1 <- ([signbit1]*XLEN) & ¬m
-            smask2 <- ([signbit2]*XLEN) & ¬m
-            RT <- (res1 | smask1)
-            RS <- (res2 | smask2)
+        round <- [0]*(XLEN*2)
+        round[XLEN*2 -n] <- 1
+        prod1 <- prod1 + round
+        prod2 <- prod2 + round
+        m <- MASK(XLEN-n, XLEN-1)
+        res1 <- prod1[XLEN-n:XLEN*2 -n -1]
+        res2 <- prod2[XLEN-n:XLEN*2 -n -1]
+        signbit1 <- prod1[0]
+        signbit2 <- prod2[0]
+        smask1 <- ([signbit1]*XLEN) & ¬m
+        smask2 <- ([signbit2]*XLEN) & ¬m
+        RT <- (res1 | smask1)
+        RS <- (res2 | smask2)
 
 Special Registers Altered:
 
@@ -71,39 +54,21 @@ Pseudo-code:
         RT <- (RT) + prod_lo
         RS <- (RS) - prod_lo
     else
-        if XLEN = 64 then
-            prod_lo <- prod[XLEN:(XLEN*2)-1]
-            res1 <- (RT) + prod_lo
-            res2 <- (RS) - prod_lo
-            round <- [0]*XLEN
-            round[XLEN -n] <- 1
-            res1 <- res1 + round
-            res2 <- res2 + round
-            signbit1 <- res1[0]
-            signbit2 <- res2[0]
-            m <- MASK(n, (XLEN-1))
-            res1 <- ROTL64(res1, XLEN-n) & m
-            res2 <- ROTL64(res2, XLEN-n) & m
-            smask1 <- ([signbit1]*XLEN) & ¬m
-            smask2 <- ([signbit2]*XLEN) & ¬m
-            RT <- (res1 | smask1)
-            RS <- (res2 | smask2)
-        else
-            res1 <- (RT) + prod
-            res2 <- (RS) - prod
-            round <- [0]*XLEN*2
-            round[XLEN*2 -n] <- 1
-            res1 <- res1 + round
-            res2 <- res2 + round
-            signbit1 <- res1[0]
-            signbit2 <- res2[0]
-            m <- MASK(XLEN-n, (XLEN-1))
-            res1 <- prod1[XLEN-n:XLEN*2 -n -1]
-            res2 <- prod2[XLEN-n:XLEN*2 -n -1]
-            smask1 <- ([signbit1]*XLEN) & ¬m
-            smask2 <- ([signbit2]*XLEN) & ¬m
-            RT <- (res1 | smask1)
-            RS <- (res2 | smask2)
+        res1 <- (RT) + prod
+        res2 <- (RS) - prod
+        round <- [0]*XLEN*2
+        round[XLEN*2 -n] <- 1
+        res1 <- res1 + round
+        res2 <- res2 + round
+        signbit1 <- res1[0]
+        signbit2 <- res2[0]
+        m <- MASK(XLEN-n, (XLEN-1))
+        res1 <- prod1[XLEN-n:XLEN*2 -n -1]
+        res2 <- prod2[XLEN-n:XLEN*2 -n -1]
+        smask1 <- ([signbit1]*XLEN) & ¬m
+        smask2 <- ([signbit2]*XLEN) & ¬m
+        RT <- (res1 | smask1)
+        RS <- (res2 | smask2)
 
 Special Registers Altered:
 
diff --git a/src/openpower/test/alu/maddsubrs_cases.py b/src/openpower/test/alu/maddsubrs_cases.py
index 326060d4..c117c2b1 100644
--- a/src/openpower/test/alu/maddsubrs_cases.py
+++ b/src/openpower/test/alu/maddsubrs_cases.py
@@ -24,7 +24,7 @@ class MADDSUBRSTestCase(TestAccumulatorBase):
 
         e = ExpectedState(pc=4)
         e.intregs[1] = 0x0000aa86
-        e.intregs[2] = 0xffffffffffff643e
+        e.intregs[2] = 0xffffffffffffe43e
         e.intregs[10] = 0x0000e6b8
         e.intregs[11] = 0x00002d41
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)