From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 30 Jul 2007 22:40:39 +0000 (-0700)
Subject: X86: Implement unsigned divide. The non-byte version ignores rdx which it shouldn't.
X-Git-Tag: m5_2.0_beta4~230
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44c3419e1a0dbf6f222955f627b45192da2ad12e;p=gem5.git

X86: Implement unsigned divide. The non-byte version ignores rdx which it shouldn't.

--HG--
extra : convert_revision : 07e5509fb8ed9d73c144d6f52951ebc02e7c0032
---

diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
index 936fa6973..5355775eb 100644
--- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
+++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
@@ -196,6 +196,53 @@ def macroop IMUL_R_P_I
     ld t2, ds, [0, t0, t7]
     mulel reg, t2, t1
 };
+
+#
+# One byte version of unsigned division
+#
+
+def macroop DIV_B_R
+{
+    div1 rax, rax, reg
+};
+
+def macroop DIV_B_M
+{
+    ld t1, ds, [scale, index, base], disp
+    div1 rax, rax, t1
+};
+
+def macroop DIV_B_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    div1 rax, rax, t1
+};
+
+#
+# Unsigned division
+#
+
+def macroop DIV_R
+{
+    divr rdx, rax, reg
+    divq rax, rax, reg
+};
+
+def macroop DIV_M
+{
+    ld t1, ds, [scale, index, base], disp
+    divr rdx, rax, t1
+    divq rax, rax, t1
+};
+
+def macroop DIV_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    divr rdx, rax, t1
+    divq rax, rax, t1
+};
 '''
 #let {{
 #    class MUL(Inst):