From: lkcl <lkcl@web>
Date: Sun, 21 Mar 2021 21:45:19 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1159
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44d144609a2420bcc7c75f0e759f30379188ef71;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index e2dd83adf..aac1c47d7 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -45,9 +45,9 @@ Form: SVL-Form (see [[isatables/fields.text]])
 
 | 0.5|6.10|11.15|16..23  | 24.25  | 26...30 |31|  name   |
 | -- | -- | --- | ------ | ------ | ------- |--| ------- |
-|OPCD| RT | RA  | SVi // | vs ms  | XO[0:4] |Rc| setvl   |
+|OPCD| RT | RA  | SVi /  | vs ms  | XO[0:4] |Rc| setvl   |
 
-Note that the immediate (`SVi`) spans 7 bits (16 to 22), and that bit 22 and 23 is reserved and must be zero.  Setting bit 22 or 23 causes an illegal exception.
+Note that the immediate (`SVi`) spans 7 bits (16 to 22), and that bit 23 is reserved and must be zero.  Setting bit 23 to 1 causes an illegal exception.
 
 `ms` - bit 25 - allows for setting of MVL.  `vs` - bit 24 - allows for
 setting of VL.