From: Tim Harris <tharris@microsoft.com>
Date: Mon, 7 Feb 2011 23:18:52 +0000 (-0800)
Subject: X86: Obey the wp bit of CR0.
X-Git-Tag: stable_2012_02_02~563
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44e5e7e0533ba2544f2d37f8e051a0422966bd9b;p=gem5.git

X86: Obey the wp bit of CR0.

If cr0.wp ("write protect" bit) is clear then do not generate page faults when
writing to write-protected pages in kernel mode.
---

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index a02c5e6a3..7b7af3288 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -634,14 +634,15 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
             // Do paging protection checks.
             bool inUser = (m5Reg.cpl == 3 &&
                     !(flags & (CPL0FlagBit << FlagShift)));
-            if ((inUser && !entry->user) ||
-                (mode == Write && !entry->writable)) {
+            CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
+            bool badWrite = (!entry->writable && (inUser || cr0.wp));
+            if ((inUser && !entry->user) || (mode == Write && badWrite)) {
                 // The page must have been present to get into the TLB in
                 // the first place. We'll assume the reserved bits are
                 // fine even though we're not checking them.
                 return new PageFault(vaddr, true, mode, inUser, false);
             }
-            if (storeCheck && !entry->writable) {
+            if (storeCheck && badWrite) {
                 // This would fault if this were a write, so return a page
                 // fault that reflects that happening.
                 return new PageFault(vaddr, true, Write, inUser, false);