From: Luke Kenneth Casson Leighton Date: Sun, 26 Jun 2022 11:38:52 +0000 (+0100) Subject: store KAIVB SPR 850 in TRAP Pipeline X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44f8a121d68fed0889d49823936371e6c3d15425;p=soc.git store KAIVB SPR 850 in TRAP Pipeline by redirecting OP_MTSPR and OP_MFSPR to it https://bugs.libre-soc.org/show_bug.cgi?id=859 --- diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index f0da82b9..c47b396e 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -58,6 +58,7 @@ class TrapMainStage(PipeModBase): super().__init__(pspec, "main") self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn]) self.fields.create_specs() + self.kaivb = Signal(64) # KAIVB SPR def trap(self, m, trap_addr, return_addr): """trap. sets new PC, stores MSR and old PC in SRR1 and SRR0 @@ -139,7 +140,7 @@ class TrapMainStage(PipeModBase): def elaborate(self, platform): m = Module() - comb = m.d.comb + comb, sync = m.d.comb, m.d.sync op = self.i.ctx.op # convenience variables @@ -201,6 +202,16 @@ class TrapMainStage(PipeModBase): # TODO: some #defines for the bits n stuff. with m.Switch(op.insn_type): + ############## + # KAIVB https://bugs.libre-soc.org/show_bug.cgi?id=859 + + with m.Case(MicrOp.OP_MTSPR): + sync += self.kaivb.eq(a_i) + + with m.Case(MicrOp.OP_MFSPR): + comb += o.data.eq(self.kaivb) + comb += o.ok.eq(1) + ############### # TDI/TWI/TD/TW. v3.0B p90-91