From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 23:18:14 +0000 (-0700)
Subject: Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
X-Git-Tag: working-ls180~1208^2~106
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44fc616fc701d698564d68a7facf210947b8bd9e;p=yosys.git

Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
---

diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index 4c1bb7d05..89586d3c3 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -55,14 +55,13 @@ module \$shiftx (A, B, Y);
       if (B_SIGNED) begin
         if (B_WIDTH < 4 || A_WIDTH <= 4)
           wire _TECHMAP_FAIL_ = 1;
-        else
-          // Since negative indices are out of the range of A
-          // and hence return 'bx, drop the sign bit
+        else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
+          // Optimisation to remove B_SIGNED if sign bit of B is constant-0
           \$__XILINX_SHIFTX #(
             .A_SIGNED(A_SIGNED),
             .B_SIGNED(0),
             .A_WIDTH(A_WIDTH),
-            .B_WIDTH($clog2(A_WIDTH*B_WIDTH)),
+            .B_WIDTH(B_WIDTH-1'd1),
             .Y_WIDTH(Y_WIDTH)
           ) _TECHMAP_REPLACE_ (
             .A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)