From: Luke Kenneth Casson Leighton Date: Tue, 10 May 2022 16:29:17 +0000 (+0100) Subject: whitespace, update memory gpio example image X-Git-Tag: opf_rfc_ls005_v1~2271 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=44ff7b9ebb8dad838c34c91209c4b7d5f0c88aef;p=libreriscv.git whitespace, update memory gpio example image --- diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn index 4e33ec0f2..7c53f9d15 100644 --- a/docs/pinmux.mdwn +++ b/docs/pinmux.mdwn @@ -543,22 +543,22 @@ not available to bank 1/2/3 peripherals. TODO: REWORK BASED ON GPIO JTAG DIAGRAMS BELOW The proposed JTAG BS chain is as follows: -* Between each peripheral and GPIO block, add a JTAG BS chain. For example -the I2C SDA line will have core o/oe/i/ie, and from JTAG the pad o/oe/i/ie will -connect to the GPIO block's ports 1-3. -* Provide a test port for the GPIO block that gives full access to configuration -(o/oe/i/ie/puen/pden) and bank select. Only allow full JTAG configuration *IF* -ban select bit 2 is set! -* No JTAG chain between WB bus and GPIO port 0 input *(not sure what to do for -this, or whether it is even needed)*. +* Between each peripheral and GPIO block, add a JTAG BS chain. For + example the I2C SDA line will have core o/oe/i/ie, and from JTAG the + pad o/oe/i/ie will connect to the GPIO block's ports 1-3. +* Provide a test port for the GPIO block that gives full access to + configuration (o/oe/i/ie/puen/pden) and bank select. Only allow full + JTAG configuration *IF* ban select bit 2 is set! +* No JTAG chain between WB bus and GPIO port 0 input *(not sure what to + do for this, or whether it is even needed)*. Such a setup would allow the JTAG chain to control the bank select when testing connectivity of the peripherals, as well as give full control to the GPIO configuration when bank select bit 2 is set. -For the purposes of muxing peripherals, bank select bit 2 is ignored. This means -that even if JTAG is handed over full control, the peripheral is still connected -to the GPIO block (via the BS chain). +For the purposes of muxing peripherals, bank select bit 2 is ignored. This +means that even if JTAG is handed over full control, the peripheral is +still connected to the GPIO block (via the BS chain). Signals for various ports: @@ -571,7 +571,7 @@ few bits, as more than 16 GPIOs per block is likely to be to big). As you can see by the above list, the GPIO block is becoming quite a complex beast. If there are suggestions to simplify or reduce some of the signals, -that will be helpful.* +that will be helpful. The diagrams below show 1-bit GPIO connectivity, as well as the 4-bit case. diff --git a/docs/pinmux/gpio_memory_example.jpg b/docs/pinmux/gpio_memory_example.jpg index 34829f070..0d799374b 100644 Binary files a/docs/pinmux/gpio_memory_example.jpg and b/docs/pinmux/gpio_memory_example.jpg differ