From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Oct 2018 19:18:32 +0000 (+0100)
Subject: c.swsp and c.fswsp predication and offset enabling
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4504a888ccb771dba82b958acd73ad1dff888090;p=riscv-isa-sim.git

c.swsp and c.fswsp predication and offset enabling
---

diff --git a/id_regs.py b/id_regs.py
index d6259cd..4dbf3b5 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -127,7 +127,10 @@ def find_registers(fname, insn, twin_predication, immed_offset):
 
     predargs = ['dest_pred'] * 4
     if immed_offset: # C.LWSP
-        predargs.append('&src_pred')
+        if immed_offset == 'LD':
+            predargs.append('&src_pred')
+        else:
+            predargs.append('&dest_pred')
         fsrc = insn in ['c_flwsp', 'c_fldsp']
         c_sp_width = {'c_lwsp': 4, 'c_ldsp': 8, 'c_lqsp': 16,
                       'c_flwsp': 4, 'c_fldsp': 8,
@@ -135,7 +138,10 @@ def find_registers(fname, insn, twin_predication, immed_offset):
                       'c_fswsp': 4, 'c_fsdsp': 8}
         iwidth = c_sp_width[insn]
         res.append('#define IMMEDWIDTH %d' % (iwidth))
-        res.append('#define SRC_PREDINT %d' % (0 if fsrc else 1))
+        if immed_offset == 'LD':
+            res.append('#define SRC_PREDINT %d' % (0 if fsrc else 1))
+        else:
+            res.append('#define DEST_PREDINT %d' % (0 if fsrc else 1))
 
     if twin_predication:
         found = None
@@ -180,10 +186,11 @@ if __name__ == '__main__':
                 txt += "#define INSN_TYPE_LOAD\n"
             elif insn in ['c_lwsp', 'c_ldsp', 'c_lqsp', 'c_flwsp', 'c_fldsp']:
                 twin_predication = True
-                immed_offset = True
+                immed_offset = 'LD'
                 txt += "\n#define INSN_TYPE_C_STACK_LD\n"
             elif insn in ['c_swsp', 'c_sdsp', 'c_sqsp', 'c_fswsp', 'c_fsdsp']:
                 twin_predication = True
+                immed_offset = 'ST'
                 txt += "\n#define INSN_TYPE_C_STACK_ST\n"
             elif insn in ['c_lw', 'c_ld', 'c_lq', 'c_flw', 'c_fld']:
                 txt += "\n#define INSN_TYPE_C_LD\n"
diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index cd63f07..5396eaa 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -37,17 +37,23 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
             xstr(INSN), INSNCODE, p->get_state()->prv,
             s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
             vlen);
+#if defined(INSN_TYPE_C_STACK_LD) || defined(INSN_TYPE_C_STACK_ST)
+    sp = insn._remap(X_SP, true, src_offs);
+#endif
 #ifdef INSN_CATEGORY_TWINPREDICATION
 #ifdef INSN_TYPE_C_STACK_LD
-    sp = insn._remap(X_SP, true, src_offs);
     src_pred = insn.predicate(sp, SRC_PREDINT, zeroingsrc);
 #else
     src_pred = insn.predicate(s_insn.SRC_REG(), SRC_PREDINT, zeroingsrc);
 #endif
 #endif
 #ifdef DEST_PREDINT
-  // use the ORIGINAL, i.e. NON-REDIRECTED, register here
+#ifdef INSN_TYPE_C_STACK_ST
+    dest_pred = insn.predicate(sp, DEST_PREDINT, zeroing);
+#else
+    // use the ORIGINAL, i.e. NON-REDIRECTED, register here
     dest_pred = insn.predicate(s_insn.DEST_REG(), DEST_PREDINT, zeroing);
+#endif
 #endif
   }
   // identify which regs have had their CSR entries set as vectorised.
@@ -120,7 +126,9 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
       if (zeroing && ((dest_pred & (1<<*dest_offs)) == 0))
       {
           // insn._rd() would be predicated: have to use insn._rd() here
+#ifndef INSN_TYPE_C_STACK_ST
           WRITE_REG(insn._DEST_REG(), 0);
+#endif
       }
 #endif
       if (vlen > 1)