From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 23:35:08 +0000 (-0800)
Subject: Add to CHANGELOG
X-Git-Tag: working-ls180~881^2^2~124^2~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=450ad0e9ba031fbeef904746ca773e3b0e21af8f;p=yosys.git

Add to CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index a49c27b05..d9d261fbc 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -53,6 +53,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "check -mapped"
     - Added checking of SystemVerilog always block types (always_comb,
       always_latch and always_ff)
+    - Added "clkpart" pass
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------