From: lkcl <lkcl@web>
Date: Sun, 19 Jun 2022 07:05:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4518852459b3ca3ea8d03dd754387724ff10594c;p=libreriscv.git

---

diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn
index 70975e582..607ff6f84 100644
--- a/openpower/sv/av_opcodes.mdwn
+++ b/openpower/sv/av_opcodes.mdwn
@@ -24,8 +24,8 @@ In-advance, the summary of base scalar operations that need to be added is:
 | abs-accumulate| result += abs (src1, src2) |
 | signed min   | result = (src1 < src2) ? src1 : src2 use bitmanip |
 | signed max   | result = (src1 > src2) ? src1 : src2  use bitmanip |
-| bitwise sel  | (a ? b : c) - use bitmanip ternary |
-| int/fp move  | GPR(RT) = FPR(FRA) and FPR(FRT) = GPR(RA) |
+| bitwise sel  | (a ? b : c) - use [[sv/bitmanip]] ternary |
+| int/fp move  | covered by [[sv/int_fp_mv]] |
 
 All other capabilities (saturate in particular) are achieved with [[sv/svp64]] modes and swizzle.  Note that minmax and ternary are added in bitmanip.