From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 3 May 2020 19:29:54 +0000 (+0200)
Subject: cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by... 
X-Git-Tag: 24jan2021_ls180~397
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=45377d9faa7722c9fb5c8efd9749ecb229d354d3;p=litex.git

cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width.
---

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index 21f7ce5d..bc106712 100644
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -29,46 +29,72 @@ class CPUNone(CPU):
     periph_buses         = []
     memory_buses         = []
 
+CPU_GCC_TRIPLE_RISCV32 = (
+    "riscv64-unknown-elf",
+    "riscv32-unknown-elf",
+    "riscv-none-embed",
+    "riscv64-linux",
+    "riscv-sifive-elf",
+    "riscv64-none-elf",
+)
+
+CPU_GCC_TRIPLE_RISCV64 = (
+    "riscv64-unknown-elf",
+    "riscv64-linux",
+    "riscv-sifive-elf",
+    "riscv64-none-elf",
+)
+
 # CPUS ---------------------------------------------------------------------------------------------
 
 from litex.soc.cores.cpu.lm32 import LM32
 from litex.soc.cores.cpu.mor1kx import MOR1KX
+from litex.soc.cores.cpu.microwatt import Microwatt
+from litex.soc.cores.cpu.serv import SERV
 from litex.soc.cores.cpu.picorv32 import PicoRV32
-from litex.soc.cores.cpu.vexriscv import VexRiscv
 from litex.soc.cores.cpu.minerva import Minerva
+from litex.soc.cores.cpu.vexriscv import VexRiscv
 from litex.soc.cores.cpu.rocket import RocketRV64
-from litex.soc.cores.cpu.microwatt import Microwatt
 from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
-from litex.soc.cores.cpu.serv import SERV
 
 CPUS = {
+    # None
     "None"        : CPUNone,
+
+    # LM32
     "lm32"        : LM32,
+
+    # OpenRisc
     "mor1kx"      : MOR1KX,
+
+    # Open Power
+    "microwatt"   : Microwatt,
+
+    # RISC-V 32-bit
+    "serv"        : SERV,
     "picorv32"    : PicoRV32,
-    "vexriscv"    : VexRiscv,
     "minerva"     : Minerva,
+    "vexriscv"    : VexRiscv,
+
+    # RISC-V 64-bit
     "rocket"      : RocketRV64,
-    "microwatt"   : Microwatt,
     "blackparrot" : BlackParrotRV64,
-    "serv"        : SERV
 }
 
 # CPU Variants/Extensions Definition ---------------------------------------------------------------
 
 CPU_VARIANTS = {
     # "official name": ["alias 1", "alias 2"],
-    "minimal" : ["min",],
-    "lite" : ["light", "zephyr", "nuttx"],
-    "standard": [None, "std"],
-    "full": [],
-    "linux" : [],
-    "linuxd" : [],
-    "linuxq" : [],
+    "minimal" :   ["min",],
+    "lite" :      ["light", "zephyr", "nuttx"],
+    "standard":   [None, "std"],
+    "full":       [],
+    "linux" :     [],
+    "linuxd" :    [],
+    "linuxq" :    [],
 }
 CPU_VARIANTS_EXTENSIONS = ["debug", "no-dsp"]
 
-
 class InvalidCPUVariantError(ValueError):
     def __init__(self, variant):
         msg = """\
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 302aa70d..9f3d4fb7 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -35,7 +35,7 @@ from migen import *
 from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
 
 CPU_VARIANTS = {
     "standard": "freechips.rocketchip.system.LitexConfig",
@@ -50,8 +50,7 @@ class BlackParrotRV64(CPU):
     human_name           = "BlackParrotRV64[ia]"
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
-                            "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV64
     linker_output_format = "elf64-littleriscv"
     nop                  = "nop"
     io_regions           = {0x50000000: 0x10000000} # origin, length
diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 2a6f21f9..64cf8666 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -9,7 +9,7 @@ from migen import *
 
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
 CPU_VARIANTS = ["standard"]
 
@@ -19,8 +19,7 @@ class Minerva(CPU):
     human_name           = "Minerva"
     data_width           = 32
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV32
     linker_output_format = "elf32-littleriscv"
     nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index b3bfc074..3f568db4 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -13,7 +13,7 @@ from migen import *
 
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
 
 
 CPU_VARIANTS = ["minimal", "standard"]
@@ -36,8 +36,7 @@ class PicoRV32(CPU):
     human_name           = "PicoRV32"
     data_width           = 32
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV64
     linker_output_format = "elf32-littleriscv"
     nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index e0100c76..f08019ff 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -36,7 +36,7 @@ from migen import *
 from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
 
 
 CPU_VARIANTS = {
@@ -69,8 +69,7 @@ class RocketRV64(CPU):
     human_name           = "RocketRV64[imac]"
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
-                            "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV64
     linker_output_format = "elf64-littleriscv"
     nop                  = "nop"
     io_regions           = {0x10000000: 0x70000000} # origin, length
diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index dbb6a1b4..739b83b6 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -8,7 +8,7 @@ from migen import *
 
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
 
 CPU_VARIANTS = ["standard"]
@@ -19,8 +19,7 @@ class SERV(CPU):
     human_name           = "SERV"
     data_width           = 32
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV32
     linker_output_format = "elf32-littleriscv"
     nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 45fc0df9..dc267ce9 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -15,7 +15,7 @@ from migen import *
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import *
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
 
 CPU_VARIANTS = {
@@ -79,8 +79,7 @@ class VexRiscv(CPU, AutoCSR):
     human_name           = "VexRiscv"
     data_width           = 32
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV32
     linker_output_format = "elf32-littleriscv"
     nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length