From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 Jun 2021 18:53:50 +0000 (+0100)
Subject: set regfile in ISACaller equal to length of initial variables
X-Git-Tag: xlen-bcd~426
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=454ff42ba907c798556b526d45ffebff807d21e8;p=openpower-isa.git

set regfile in ISACaller equal to length of initial variables
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 9ab9a67f..e3ecbed6 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -98,7 +98,7 @@ class GPR(dict):
         self.sd = decoder
         self.isacaller = isacaller
         self.svstate = svstate
-        for i in range(32):
+        for i in range(len(regfile)):
             self[i] = SelectableInt(regfile[i], 64)
 
     def __call__(self, ridx):
@@ -123,12 +123,7 @@ class GPR(dict):
         """ XXX currently not used
         """
         rnum = self._get_regnum(attr)
-        # XXX TODO, this needs sorting! (1) reverse gear for mapreduce
-        # and (2) when doing element-width overrides.  used by
-        # GPR(x) or GPR[x] in pseudocode
-        offs = self.svstate.srcstep
-        log("GPR getitem TODO mapreduce reverse-gear", attr, rnum,
-             "srcoffs", offs)
+        log("GPR getitem", attr, rnum)
         return self.regfile[rnum]
 
     def dump(self, printout=True):