From: lkcl <lkcl@web>
Date: Sat, 9 Jan 2021 22:25:21 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~504
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=455372b86eb0e8d8a7c19c8eb8be1dbc7663d9e2;p=libreriscv.git

---

diff --git a/openpower/sv/propagation.mdwn b/openpower/sv/propagation.mdwn
index 68c8615a8..c55a38165 100644
--- a/openpower/sv/propagation.mdwn
+++ b/openpower/sv/propagation.mdwn
@@ -113,7 +113,7 @@ for specifying to which registers the swizzle is to be applied, and
 there is only 17 bit suite to indicate the instructions to which the
 swizzle applies.
 
-The bits in rhe svp64 `RM` field are interpreted as a pair of 12 bit
+The bits in the svp64 `RM` field are interpreted as a pair of 12 bit
 swizzles
 
 | 0.5| 6.8 | 9.11| 12.14 | 15.31 |  name   |