From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 20:21:21 +0000 (-0700)
Subject: Fix spacing
X-Git-Tag: working-ls180~1075^2^2~33^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=455da572723e4f19ddc1d636b700a5fe1e975fbb;p=yosys.git

Fix spacing
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index e2bf3c854..01b10f392 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 (
 	input        WCK,
 	input  [3:0] RAD,
 	/* (* abc_arrival=<TODO> *) */
-    output [3:0] DO
+	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";