From: Luke Kenneth Casson Leighton Date: Fri, 16 Sep 2022 11:31:45 +0000 (+0100) Subject: add SPR notes X-Git-Tag: opf_rfc_ls005_v1~403 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=456c2a3d57483d4d50de0ed569b3bf263c61eddb;p=libreriscv.git add SPR notes --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 6ff623b83..be389e575 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -192,11 +192,13 @@ at least the next decade (including if added on VSX) **Simple-V SPRs** * **SVSTATE** - Vectorisation State sufficient for Precise-Interrupt - Context-switching and no adverse latency. + Context-switching and no adverse latency, it may be considered to + be a "Sub-PC" and as such absolutely must be treated with the same + respect and priority as MSR and PC. * **SVSRR0** - identical in purpose to SRR0/1: storing SVSTATE on context-switch along-side MSR and PC. * **SVSHAPE0-3** - these are 32-bit and may be grouped in pairs, they REMAP - (shape) the Vectors + (shape) the Vectors[^svshape] * **SVLR** - again similar to LR for exactly the same purpose, SVSTATE is swapped with SVLR by SV-Branch-Conditional for exactly the same reason that NIA is swapped with LR @@ -1090,3 +1092,4 @@ operations. [^vsx256]: imagine a hypothetical future VSX-256 using the exact same instructions as VSX. the binary incompatibility introducrd would catastrophically **and retroactively** damage existing IBM POWER8,9,10 hardware's reputation and that of Power ISA overall. [^autovec]: Compiler auto-vectorisation for best exploitation of SIMD and Vector ISAs on Scalar programming languages (c, c++) is an Indusstry-wide known-hard decades-long problem. Cross-reference the number of hand-optimised assembler algorithms. [^hphint]: intended for use when the compiler has determined the extent of Memory or register aliases in loops: `a[i] += a[i+4]` would necessitate a Vertical-First hphint of 4 +[^svshape]: although SVSHAPE0-3 should, realistically, be regarded as high a priority as SVSTATE, and given corresponding SVSRR and SVLR equivalents, it was felt that having to context-switch **five** SPRs on Interrupts and function calls was too much.