From: Shriya Sharma Date: Wed, 18 Oct 2023 11:36:45 +0000 (+0100) Subject: correction on syntax of biginteger analysis SVP64 snippet, X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=456ee3f8e2e39c20454aeebb567f6454dc3d4566;p=libreriscv.git correction on syntax of biginteger analysis SVP64 snippet, added more to description of dsrd` --- diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index 8d94d2ecd..12923cb5e 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -300,10 +300,10 @@ vector data offset by one. Given that all three instructions (`srd`, `sld`, `or`) are an SVP64 type `RM-1P-2S1D` and are `EXTRA3`, it is possible to reference the full 128 64-bit registers (r0-r127): - subfic t1, t0, 64 # compute 64-s (s in t0) - sv.srd r8.v, r24.v, t0 # shift each element of r24.v up by s - sv.sld r16.v, r25.v, t1 # offset start of vector by one (r25) - sv.or r8.v, r8.v, r16.v # OR two parts together + subfic t1, t0, 64 # compute 64-s (s in t0) + sv.srd *r8, *r24, t0 # shift each element of r24 vector up by s + sv.sld *r16, *r25, t1 # offset start of vector by one (r25) + sv.or *r8, *r8, *r16 # OR two parts together Predication with zeroing may be utilised on sld to ensure that the last element is zero, avoiding over-run. @@ -337,7 +337,14 @@ may be applied, which only requires `ROT64`: ``` The trick here is that the *entirety* of `RA` is rotated, -the +then parts of it are masked into the destinations. +RC, if also properly masked, can be ORed into RT, as +long as the bits of RC are in the right place. +The really interesting bit is that when Vectorised, +the upper bits (now in RS) *are* in the right bit-positions +to be ORed into the second `dsrd` operation. This allows +us to create a chain `sv.dsrd`. + For larger shift amounts beyond an element bitwidth standard register move operations may be used, or, if the shift amount is static, to reference an alternate starting point in