From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Thu, 7 Mar 2019 05:19:58 +0000 (-0800)
Subject: Add submodule names explicitly for easier yosys graph reading.
X-Git-Tag: div_pipeline~2340
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=457112fb323b917cd582d868e0cdff5ef3eef20d;p=soc.git

Add submodule names explicitly for easier yosys graph reading.
---

diff --git a/TLB/src/Cam.py b/TLB/src/Cam.py
index 5c80149d..09a0a749 100644
--- a/TLB/src/Cam.py
+++ b/TLB/src/Cam.py
@@ -56,11 +56,11 @@ class Cam():
     def elaborate(self, platform=None):
         m = Module()
         # Encoder checks for multiple matches
-        m.submodules += self.encoder
+        m.submodules.encoder = self.encoder
         # Priority Encoder is used to select output address
-        m.submodules += self.p_encoder
+        m.submodules.p_encoder = self.p_encoder
         # Decoder is used to select which entry will be written to
-        m.submodules += self.decoder
+        m.submodules.decoder = self.decoder
         # Don't forget to add all entries to the submodule list
         entry_array = self.entry_array
         m.submodules += entry_array
@@ -94,6 +94,7 @@ class Cam():
                 m.d.comb += self.p_encoder.i[index].eq(entry_array[index].match)
 
             # If the priority encoder recieves an input of 0
+            # If n is 1 then the output is not valid
             with m.If(self.p_encoder.n):
                 m.d.comb += [
                     self.read_warning.eq(0),