From: Luke Kenneth Casson Leighton Date: Wed, 11 Mar 2020 23:42:35 +0000 (+0000) Subject: Re: [libre-riscv-dev] processor and soc naming X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=458841942bfc57c1d287d99c902b6c831bff46a1;p=libre-riscv-dev.git Re: [libre-riscv-dev] processor and soc naming --- diff --git a/6c/ba74a53529a9efb4a95abb0701d34b4371951c b/6c/ba74a53529a9efb4a95abb0701d34b4371951c new file mode 100644 index 0000000..4998b01 --- /dev/null +++ b/6c/ba74a53529a9efb4a95abb0701d34b4371951c @@ -0,0 +1,72 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Wed, 11 Mar 2020 23:43:00 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jCB07-0004Tg-Mo; Wed, 11 Mar 2020 23:42:59 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jCB05-0004Ta-NM + for libre-riscv-dev@lists.libre-riscv.org; Wed, 11 Mar 2020 23:42:57 +0000 +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lkcl.net; + s=201607131; + h=Content-Type:To:Subject:Message-ID:Date:From:References:In-Reply-To:MIME-Version; + bh=Vrt/zS//h4UUgPKpXOho2BrXWctUzcMMm/yydWa5axA=; + b=KuSCqK3P6YNexqjqmpm545Td+yYjWp6uUXGaOvurpK60DxM5h2XhQjK1XsA28V3aEKuB51ax2VGJAb7uIzc5Bwf0xOQbrvt1126GlEegIL05dAr8PASG3e0wuTdLN+BjqGH1tGwmA5Y4mtUaAw9eN5ig+pjRl67tjsonXrs4sbQ=; +Received: from mail-lj1-f179.google.com ([209.85.208.179]) + by lkcl.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.84_2) (envelope-from ) id 1jCB05-0005Mf-9t + for libre-riscv-dev@lists.libre-riscv.org; Wed, 11 Mar 2020 23:42:57 +0000 +Received: by mail-lj1-f179.google.com with SMTP id g12so4338246ljj.3 + for ; + Wed, 11 Mar 2020 16:42:41 -0700 (PDT) +X-Gm-Message-State: ANhLgQ0avyn8rQAQ/4dGSuwIYZV4U5kck49tkCtXjcvTzFCR346Gjjkn + sGcwASj3bPt64T6Gx9QFhpswuuvWA01TEPVszL4= +X-Google-Smtp-Source: ADFU+vsTgyp1uDrUFuuS2a57rqFHWTUaY+ArujUac5XhqC3ifh7BVW1OSqcFxvUh+xu+k9lesSssuyxNQJFlDyYw4KI= +X-Received: by 2002:a2e:918d:: with SMTP id f13mr3560325ljg.191.1583970156386; + Wed, 11 Mar 2020 16:42:36 -0700 (PDT) +MIME-Version: 1.0 +Received: by 2002:ab3:4911:0:0:0:0:0 with HTTP; Wed, 11 Mar 2020 16:42:35 + -0700 (PDT) +In-Reply-To: +References: <327623BB-9D89-4666-A984-5B48FC2EC262@gatech.edu> + + + + +From: Luke Kenneth Casson Leighton +Date: Wed, 11 Mar 2020 23:42:35 +0000 +X-Gmail-Original-Message-ID: +Message-ID: +To: Libre-RISCV General Development +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] processor and soc naming +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +T24gV2VkbmVzZGF5LCBNYXJjaCAxMSwgMjAyMCwgSmFjb2IgTGlmc2hheSA8cHJvZ3JhbW1lcmph +a2VAZ21haWwuY29tPgp3cm90ZToKPgo+Cj4gSSB3YXMgdGhpbmtpbmcgd2UnZCBqdXN0IHNldCB0 +aGVtIGFsbCB0byByZWRpcmVjdCB0byAocGVyaGFwcyBzcGVjaWZpYwo+IHBhZ2VzIGluKSBsaWJy +ZS1zb2Mub3JnLgoKCnl5ZWFoIHRoYXQncyBhIHJlYWxseSBnb29kIGlkZWEuCgoKPgo+CgotLSAK +LS0tCmNyb3dkLWZ1bmRlZCBlY28tY29uc2Npb3VzIGhhcmR3YXJlOiBodHRwczovL3d3dy5jcm93 +ZHN1cHBseS5jb20vZW9tYTY4Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f +X19fX19fX19fCmxpYnJlLXJpc2N2LWRldiBtYWlsaW5nIGxpc3QKbGlicmUtcmlzY3YtZGV2QGxp +c3RzLmxpYnJlLXJpc2N2Lm9yZwpodHRwOi8vbGlzdHMubGlicmUtcmlzY3Yub3JnL21haWxtYW4v +bGlzdGluZm8vbGlicmUtcmlzY3YtZGV2Cg==