From: Kevin Lim <ktlim@umich.edu>
Date: Tue, 7 Nov 2006 18:53:49 +0000 (-0500)
Subject: Fix compile error.
X-Git-Tag: m5_2.0_beta2~53^2~3^2~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4589ec55aed596a4b0b7d81779f2b4665643d223;p=gem5.git

Fix compile error.

--HG--
extra : convert_revision : a4c4195bc07383149a56907f26d327a4bfa77c26
---

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 828c2b4ca..ccb467394 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -363,8 +363,8 @@ class OzoneCPU : public BaseCPU
 
     bool interval_stats;
 
-    AlphaITB *itb;
-    AlphaDTB *dtb;
+    TheISA::ITB *itb;
+    TheISA::DTB *dtb;
     System *system;
     PhysicalMemory *physmem;
 #endif
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index c4d16b3af..a71795851 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -122,7 +122,7 @@ struct OzoneThreadState : public ThreadState {
 
     MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
+        return miscRegFile.readRegWithEffect(misc_reg, tc);
     }
 
     void setMiscReg(int misc_reg, const MiscReg &val)