From: Ruben Undheim Date: Fri, 12 Oct 2018 18:58:37 +0000 (+0200) Subject: Support for 'modports' for System Verilog interfaces X-Git-Tag: yosys-0.9~440^2~3 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=458a94059e6738d93a87ddb9af282d0e1d28791d;p=yosys.git Support for 'modports' for System Verilog interfaces --- diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 256c08776..10fd5277a 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1118,7 +1118,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict parameters, dict interfaces, bool mayfail) +RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict parameters, dict interfaces, dict modports, bool mayfail) { AstNode *new_ast = NULL; std::string modname = derive_common(design, parameters, &new_ast, mayfail); @@ -1143,14 +1143,46 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict 0) { + std::string interface_modport = modports.at(intfname).str(); + AstModule *ast_module_of_interface = (AstModule*)intfmodule; + AstNode *ast_node_of_interface = ast_module_of_interface->ast; + for (auto &ch : ast_node_of_interface->children) { + if (ch->type == AST_MODPORT) { + if (ch->str == interface_modport) { + modport = ch; + } + } + } + } for (auto &wire_it : intfmodule->wires_){ AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true))); std::string origname = log_id(wire_it.first); std::string newname = intfname + "." + origname; wire->str = newname; - wire->is_input = true; - wire->is_output = true; - new_ast->children.push_back(wire); + if (modport != NULL) { + bool found_in_modport = false; + for (auto &ch : modport->children) { + if (ch->type == AST_MODPORTMEMBER) { + std::string compare_name = "\\" + origname; + if (ch->str == compare_name) { + found_in_modport = true; + wire->is_input = ch->is_input; + wire->is_output = ch->is_output; + break; + } + } + } + if (found_in_modport) { // If not found in modport, do not create port + new_ast->children.push_back(wire); + } + } + else { // If no modport, set inout + wire->is_input = true; + wire->is_output = true; + new_ast->children.push_back(wire); + } } } diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 6b93832b4..8187b1ac6 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -145,6 +145,8 @@ namespace AST AST_INTERFACE, AST_INTERFACEPORT, AST_INTERFACEPORTTYPE, + AST_MODPORT, + AST_MODPORTMEMBER, AST_PACKAGE }; @@ -287,7 +289,7 @@ namespace AST bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; ~AstModule() YS_OVERRIDE; RTLIL::IdString derive(RTLIL::Design *design, dict parameters, bool mayfail) YS_OVERRIDE; - RTLIL::IdString derive(RTLIL::Design *design, dict parameters, dict interfaces, bool mayfail) YS_OVERRIDE; + RTLIL::IdString derive(RTLIL::Design *design, dict parameters, dict interfaces, dict modports, bool mayfail) YS_OVERRIDE; std::string derive_common(RTLIL::Design *design, dict parameters, AstNode **new_ast_out, bool mayfail); void reprocess_module(RTLIL::Design *design, dict local_interfaces) YS_OVERRIDE; RTLIL::Module *clone() const YS_OVERRIDE; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 1dd1a9130..d87163dc2 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -853,6 +853,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_GENIF: case AST_GENCASE: case AST_PACKAGE: + case AST_MODPORT: + case AST_MODPORTMEMBER: break; case AST_INTERFACEPORT: { // If a port in a module with unknown type is found, mark it as "is_interface=true" @@ -865,6 +867,33 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->port_input = true; wire->port_output = true; wire->set_bool_attribute("\\is_interface"); + if (children.size() > 0) { + for(size_t i=0; itype == AST_INTERFACEPORTTYPE) { + std::string name_type = children[i]->str; + size_t ndots = std::count(name_type.begin(), name_type.end(), '.'); + if (ndots == 0) { + wire->attributes["\\interface_type"] = name_type; + } + else { + std::stringstream name_type_stream(name_type); + std::string segment; + std::vector seglist; + while(std::getline(name_type_stream, segment, '.')) { + seglist.push_back(segment); + } + if (ndots == 1) { + wire->attributes["\\interface_type"] = seglist[0]; + wire->attributes["\\interface_modport"] = seglist[1]; + } + else { + log_error("More than two '.' in signal port type (%s)\n", name_type.c_str()); + } + } + break; + } + } + } wire->upto = 0; } break; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 0ff5d576e..a6f37008a 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -61,6 +61,7 @@ namespace VERILOG_FRONTEND { bool noassert_mode, noassume_mode, norestrict_mode; bool assume_asserts_mode, assert_assumes_mode; bool current_wire_rand, current_wire_const; + bool current_modport_input, current_modport_output; std::istream *lexin; } YOSYS_NAMESPACE_END @@ -1325,7 +1326,16 @@ opt_stmt_label: TOK_ID ':' | /* empty */; modport_stmt: - TOK_MODPORT TOK_ID modport_args_opt ';' + TOK_MODPORT TOK_ID { + AstNode *modport = new AstNode(AST_MODPORT); + ast_stack.back()->children.push_back(modport); + ast_stack.push_back(modport); + modport->str = *$2; + delete $2; + } modport_args_opt { + ast_stack.pop_back(); + log_assert(ast_stack.size() == 2); + } ';' modport_args_opt: '(' ')' | '(' modport_args optional_comma ')'; @@ -1334,11 +1344,19 @@ modport_args: modport_arg | modport_args ',' modport_arg; modport_arg: - modport_type_token TOK_ID | + modport_type_token TOK_ID { + AstNode *modport_member = new AstNode(AST_MODPORTMEMBER); + ast_stack.back()->children.push_back(modport_member); + modport_member->str = *$2; + modport_member->is_input = current_modport_input; + modport_member->is_output = current_modport_output; + delete $2; + } | TOK_ID + /* FIXME for TOK_ID without modport_type_token */ modport_type_token: - TOK_INPUT | TOK_OUTPUT + TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;} assert: opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' { diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index fadac0872..07dd4bfa0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -654,7 +654,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, dict , bool mayfail) +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict, dict, dict, bool mayfail) { if (mayfail) return RTLIL::IdString(); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 8a2b0a4f3..276540aa1 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -907,7 +907,7 @@ public: Module(); virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, bool mayfail = false); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, dict interfaces, bool mayfail = false); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, dict interfaces, dict modports, bool mayfail = false); virtual size_t count_id(RTLIL::IdString id); virtual void reprocess_module(RTLIL::Design *design, dict local_interfaces); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index dd4341127..f2f0d6e5b 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -174,6 +174,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check cell->type = cell->type.str().substr(pos_type + 1); } dict interfaces_to_add_to_submodule; + dict modports_used_in_submodule; if (design->modules_.count(cell->type) == 0) { @@ -224,6 +225,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // some lists, so that they can be replaced further down: for (auto &conn : cell->connections()) { if(mod->wires_.count(conn.first) != 0 && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list + //const pool &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type"); + //for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module + //} + const pool &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_modport"); + std::string interface_modport = ""; + for (auto &d : interface_modport_pool) { + interface_modport = "\\" + d; + } if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) { std::string interface_name_str = conn.second.bits()[0].wire->name.str(); interface_name_str.replace(0,23,""); @@ -247,6 +256,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check } connections_to_remove.push_back(conn.first); interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name); + if (interface_modport != "") { + modports_used_in_submodule[conn.first] = interface_modport; + } } else will_do_step = true; } @@ -322,7 +334,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check continue; } - cell->type = mod->derive(design, cell->parameters, interfaces_to_add_to_submodule); + cell->type = mod->derive(design, cell->parameters, interfaces_to_add_to_submodule, modports_used_in_submodule); cell->parameters.clear(); did_something = true; diff --git a/tests/simple/svinterface1.sv b/tests/simple/svinterface1.sv index 779d50c14..64383a06c 100644 --- a/tests/simple/svinterface1.sv +++ b/tests/simple/svinterface1.sv @@ -19,7 +19,7 @@ module TopModule( assign MyInterfaceInstance.setting = 1; - assign MyInterfaceInstance.other_setting[2:0] = 3'b101; +// assign MyInterfaceInstance.other_setting[2:0] = 3'b101; endmodule @@ -32,13 +32,25 @@ interface MyInterface #( logic [1:0] mysig_out; + modport submodule1 ( + input setting, + output other_setting, + output mysig_out + ); + + modport submodule2 ( + input setting, + output other_setting, + input mysig_out + ); + endinterface module SubModule1( input logic clk, input logic rst, - MyInterface u_MyInterface, + MyInterface.submodule1 u_MyInterface, input logic [1:0] sig ); @@ -68,9 +80,11 @@ module SubModule2( input logic clk, input logic rst, - MyInterface u_MyInterfaceInSub2, + MyInterface.submodule2 u_MyInterfaceInSub2, input logic [1:0] sig ); + assign u_MyInterfaceInSub2.other_setting[2:0] = 9; + endmodule