From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 Jun 2020 09:56:35 +0000 (+0100)
Subject: add attempt at mapping between PortInterface and LoadStoreUnitInterface
X-Git-Tag: div_pipeline~277
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4595b9445697be40c332ef91bb9bdcb74e896629;p=soc.git

add attempt at mapping between PortInterface and LoadStoreUnitInterface
---

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
new file mode 100644
index 00000000..7b2e6d07
--- /dev/null
+++ b/src/soc/experiment/pi2ls.py
@@ -0,0 +1,21 @@
+"""
+    PortInterface                LoadStoreUnitInterface
+
+    is_ld_i/1                    x_ld_i
+    is_st_i/1                    x_st_i
+
+    data_len/4                   x_mask/16  (translate using LenExpand)
+
+    busy_o/1                     most likely to be x_busy_o
+    go_die_i/1                   rst?
+    addr.data/48                 x_addr_i[4:] (x_addr_i[:4] goes into LenExpand)
+    addr.ok/1                    probably x_valid_i & ~x_stall_i
+
+    addr_ok_o/1                  no equivalent.  *might* work using x_stall_i
+    addr_exc_o/2(?)              m_load_err_o and m_store_err_o
+
+    ld.data/64                   m_ld_data_o
+    ld.ok/1                      probably implicit, when x_busy drops low
+    st.data/64                   x_st_data_i
+    st.ok/1                      probably kinda redundant, set to x_st_i
+"""