From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Jun 2020 12:36:14 +0000 (+0100)
Subject: allow ALU / Logical ops to select RS as 1st operand
X-Git-Tag: div_pipeline~689
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4598ebf48a54756ae37e189b684ffbee88bdb07c;p=soc.git

allow ALU / Logical ops to select RS as 1st operand
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 81ab7143..d12566d0 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -49,6 +49,11 @@ class DecodeA(Elaboratable):
                   (self.reg_out.data == Const(0, 5))):
             comb += self.immz_out.eq(1)
 
+        # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
+        with m.If(self.sel_in == In1Sel.RS):
+            comb += self.reg_out.data.eq(self.dec.RS)
+            comb += self.reg_out.ok.eq(1)
+
         # decode SPR1 based on instruction type
         op = self.dec.op
         # BC or BCREG: potential implicit register (CTR)
diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 05353d2f..cdf5c591 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -171,6 +171,7 @@ class In1Sel(Enum):
     RA = 1
     RA_OR_ZERO = 2
     SPR = 3
+    RS = 4  # for some ALU/Logical operations
 
 
 @unique